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LogisimRevisited

Components

Component reference

41 components in 6 libraries, matching the Logisim 2.7.1 libraries.

Wiring

WiringInput PinInteractive input source and output monitor in Logisim; toggle 0 and 1 live with the Poke tool or inspect multi-bit buses. WiringOutput Pin / ProbeRead-only signal monitor that displays the live 4-state logic value (0, 1, Z, or E) of any wire or multi-bit bus. WiringTunnelConnect wires across a schematic by name without drawing long crossing lines; all Tunnels with the same case-sensitive Label share one electrical net. WiringSplitterPack individual 1-bit wires into a multi-bit bus or unpack a bus into individual bit branches (bit0 through bit7). WiringClockPeriodic square-wave signal generator that alternates between 0 and 1 to drive rising-edge flip-flops, registers, and counters. WiringConstantSupplies a fixed 1-bit (0 or 1) or multi-bit hexadecimal constant value to a wire or bus. WiringPower (1)Schematic upward-triangle Vcc symbol that supplies a permanent logic High (all 1s) to a wire or bus. WiringGround (0)Schematic three-bar ground symbol that supplies a permanent logic Low (all 0s) to a wire or bus.

I/O

I/OButtonMomentary push button that outputs 1 while pressed with the Poke tool and returns to 0 when released. I/OLEDVisual 1-bit indicator lamp that lights up bright red/green when its input wire is driven High (1). I/O7-SegmentComplete 7-Segment Display pinout in Logisim: top pins (g, f, a, b) and bottom pins (e, d, c, dp) that illuminate each segment when driven High (1). I/OHex DisplayBuilt-in hexadecimal 7-segment display that takes a single 4-bit bus input on its bottom Hex pin and automatically renders digits 0–9 and A–F.

Gates

GatesNOTLogical inverter that flips 0 to 1 and 1 to 0 bit-by-bit across single wires or multi-bit buses. GatesBufferPasses its input logic value unchanged (0 → 0, 1 → 1) while converting floating Z inputs into explicit Error (E) states. GatesTri-State BufferThree-state bus driver that passes its input to the output when Enable is 1 and disconnects to high-impedance Floating (Z) when Enable is 0. GatesTri-State NOTInverting tri-state driver that outputs ~A when Enable is 1 and disconnects to high-impedance Floating (Z) when Enable is 0. GatesANDOutputs 1 only when every active input is 1 (Y = A · B); outputs a controlling 0 immediately if any input is 0. GatesOROutputs 1 when at least one active input is 1 (Y = A + B); outputs 0 only when all active inputs are 0. GatesNANDUniversal inverted-AND gate (Y = ~(A · B)) that outputs 0 only when all active inputs are 1, and outputs 1 if any input is 0. GatesNORUniversal inverted-OR gate (Y = ~(A + B)) that outputs 1 only when all active inputs are 0, and outputs 0 if any input is 1. GatesXORExclusive OR gate (Y = A ⊕ B = A·~B + ~A·B) in Logisim: 2-input truth table, multi-input odd-parity behavior, and binary adder design. GatesXNORExclusive NOR (logical equivalence) gate (Y = ~(A ⊕ B)) that outputs 1 when two inputs are equal or when an even number of inputs are 1. GatesOdd ParityIEEE rectangular parity box (labeled 2k+1) that outputs 1 when an odd number of active inputs are High (1). GatesEven ParityIEEE rectangular parity box (labeled 2k) that outputs 1 when an even number of active inputs (0, 2, 4, ...) are High (1).

Plexers

PlexersMUXRoutes one of 2^S data inputs (D0..D(2^S-1)) to output Y based on the binary Select input S on the bottom edge. PlexersDEMUXRoutes a single data input D to the selected output Y[S] while driving all unselected outputs to 0. PlexersDecoderConverts an S-bit binary Select input into a one-hot code across 2^S output lines (asserting exactly Y[S] = 1). PlexersPriority EncoderOutputs the S-bit binary index (Q) of the highest-numbered active input line (D0..D(2^S-1)) along with a Group Signal (GS) flag.

Arithmetic

ArithmeticAdderComputes the N-bit binary sum of operands A and B plus a 1-bit Carry-In (cin), outputting Sum and a 1-bit Carry-Out (cout). ArithmeticSubtractorComputes N-bit binary subtraction (A - B - bin), producing an N-bit Difference (Diff) and a 1-bit Borrow-Out (bout). ArithmeticMultiplierMultiplies two N-bit binary integers A and B and outputs the lower N bits of the product (Prod). ArithmeticComparatorCompares two N-bit signed integers A and B and asserts exactly one of its three 1-bit outputs: A>B, A=B, or A<B. ArithmeticNegatorComputes the N-bit two's complement arithmetic negation (-A = ~A + 1) of its input bus. ArithmeticShifterShifts an N-bit data input A left or right by the binary shift distance on pin sh (Logical Left, Logical Right, or Arithmetic Right).

Memory

MemoryD Flip-FlopRising-edge triggered 1-bit Data Flip-Flop that captures input D on the 0 → 1 Clock transition and outputs Q and ~Q. MemoryT Flip-FlopT Flip-Flop in Logisim: characteristic truth table (T=0 hold, T=1 toggle on rising CLK edge), pinout (CLK, T, RST, Q, ~Q), and frequency divider / ripple counter design. MemoryJ-K Flip-FlopUniversal rising-edge flip-flop in Logisim: J=0,K=0 holds, J=0,K=1 resets (0), J=1,K=0 sets (1), and J=1,K=1 toggles ~Q without an invalid state. MemoryS-R Flip-FlopClocked Set-Reset (S-R) Flip-Flop in Logisim: complete characteristic and excitation truth table (Hold, Reset, Set, and 1,1 state), rising-edge CLK triggering, and asynchronous RST pin. MemoryRegisterStores an N-bit multi-bit word from input D onto output Q on the rising Clock edge whenever Enable (EN) is High (1). MemoryCounterSynchronous N-bit binary up-counter that increments Q by 1 on each rising Clock edge and asserts overflow (ovf) at its maximum count (2^N - 1). MemoryROMCombinational Read-Only Memory lookup table indexed by an S-bit address bus (A) that outputs the stored N-bit hexadecimal word on D.