Components / Wiring
Clock Component in Logisim
Periodic square-wave signal generator that alternates between 0 and 1 to drive rising-edge flip-flops, registers, and counters.
| Library | Wiring |
|---|---|
| Type name | Clock |
| Pins and defaults | out0, width 1, value 0/1 |
How the Clock Works in Logisim
The Clock component generates the heartbeat for sequential digital circuits. Its 1-bit output toggles between Low (0) and High (1), producing the rising edges (0 → 1 transitions) that trigger D, T, J-K, and S-R flip-flops as well as Registers and Counters.
You can step the Clock manually by clicking it with the Poke tool—each click flips its output between 0 and 1—or let the simulator step clocks automatically when you test counters and state machines.
In larger sequential designs, wire the Clock output into a Tunnel labeled CLK so every flip-flop and register in the circuit receives a clean, synchronized clock edge without crossing wires.
Tip: When debugging a sequential circuit, step the Clock manually with the Poke tool so you can watch each rising edge (0 → 1) update Q one cycle at a time.
Clock Pins & Pinout
| Pin | Direction | Width | Location & Role |
|---|---|---|---|
| out0 (Clock) | Output | 1 bit | Located at (0, 0), facing east by default. Outputs 0 or 1 and toggles on each clock step or Poke click. |
Clock Truth Table & Behavior
| Previous Clock | Current Clock | Transition Type | Sequential Effect |
|---|---|---|---|
| 0 | 1 | Rising edge (↑) | Flip-flops, Registers, and Counters sample inputs and update Q |
| 1 | 0 | Falling edge (↓) | Rising-edge components hold their current stored state Q |
| 0 or 1 | Unchanged | Steady level | State is held steady (unless asynchronous RST=1) |