T Flip-Flop (Toggle Flip-Flop) in Logisim

The T Flip-Flop (Toggle Flip-Flop) is a 1-bit edge-triggered sequential memory component whose state flips (0 → 1 or 1 → 0) on the rising edge (0 → 1 transition) of the Clock (CLK) whenever its Toggle input (T) is High (1). When T is Low (0), the flip-flop holds its current state Q unchanged across clock edges.

Its characteristic equation is Q(next) = T ⊕ Q = (~T · Q) + (T · ~Q). In Logisim Revisited, if the T pin is left unconnected (floating Z), it defaults to 1 (toggle enabled), so a freshly placed T Flip-Flop toggles on every rising clock pulse automatically.

Pin layout in Logisim: On the left edge, the top input with the triangle marker is CLK (at offset -40, 0) and the lower input is T (at offset -40, 20). On the bottom edge is the active-high asynchronous Reset pin RST (at offset -20, 30), which immediately clears Q = 0 and ~Q = 1 whenever RST = 1. On the right edge are the state output Q (top, offset 0, 0) and its complement ~Q (bottom, offset 0, 20).

Divide-by-2 frequency divider & ripple counters: Tying T = 1 turns a T Flip-Flop into a divide-by-2 frequency divider—its output Q changes state once per rising clock edge, so Q completes one full 0-1-0 period for every two clock periods. Cascading multiple T Flip-Flops in series (or feeding each stage’s T input with the AND of all lower-order Q outputs) is the standard way to build a binary ripple or synchronous up-counter.

Tip: To build a divide-by-2 frequency divider or binary counter stage in Logisim, tie the T input to a Constant 1 (or Power) and feed your clock pulse into CLK.