Components / Memory
D Flip-Flop in Logisim
Rising-edge triggered 1-bit Data Flip-Flop that captures input D on the 0 → 1 Clock transition and outputs Q and ~Q.
| Library | Memory |
|---|---|
| Type name | D Flip-Flop |
| Pins and defaults | clk CLK (-40, 0), d D (-40, 20), rst RST (-20, 30), q Q (0, 0), qn ~Q (0, 20) |
How the D Flip-Flop Works in Logisim
The D Flip-Flop (Data or Delay Flip-Flop) is the fundamental 1-bit synchronous storage element. On each rising edge (0 → 1 transition) of the Clock input (CLK), it samples the value on the D input (0 or 1) and stores it on output Q, while driving the complement on ~Q.
Between rising clock edges, changes on D have no effect on Q—the flip-flop holds its stored bit steady. Driving the bottom asynchronous Reset pin (RST) High (1) immediately clears Q to 0 (and ~Q to 1) regardless of the Clock state.
Tip: Wire ~Q back to D to make a D Flip-Flop toggle its state on every rising clock edge, or chain several D Flip-Flops in series (Q into the next D) to build a shift register.
D Flip-Flop Pins & Pinout
| Pin | Direction | Width | Location & Role |
|---|---|---|---|
| clk (CLK) | Input (Upper-left, triangle) | 1 bit | Offset (-40, 0). Rising-edge (0 → 1) clock trigger input. |
| d (D) | Input (Lower-left) | 1 bit | Offset (-40, 20). Data bit captured on the rising clock edge. |
| rst (RST) | Input (Bottom edge) | 1 bit | Offset (-20, 30). Asynchronous active-high reset: forces Q = 0 when RST = 1. |
| q (Q) | Output (Upper-right) | 1 bit | Offset (0, 0). Stored 1-bit state Q. |
| qn (~Q) | Output (Lower-right) | 1 bit | Offset (0, 20). Complement of stored state (~Q). |
D Flip-Flop Truth Table & Behavior
| RST | CLK | D | Q(next) | ~Q(next) | Behavior |
|---|---|---|---|---|---|
| 1 | X | X | 0 | 1 | Asynchronous Reset (immediate) |
| 0 | ↑ (0 → 1) | 0 | 0 | 1 | Capture 0 on rising clock edge |
| 0 | ↑ (0 → 1) | 1 | 1 | 0 | Capture 1 on rising clock edge |
| 0 | 0, 1, or ↓ | X | Q | ~Q | Hold previous state |